2
FN8215.2
February 25, 2008
Block Diagram
Pin Description
SDA
SCL
WP
2-WIRE
I
OUT
INTERFACE
A2, A1, A0
DAC
ADC
LOOK-UP
TABLE
CONTROL
AND STATUS
MUX
MUX
TEMPERATURE
SENSOR
VOLTAGE
REFERENCE
PIN
NUMBER
PIN
NAME
DESCRIPTION
1
A0
Device Address Select Pin 0. This pin determines the LSB of the device address
required to communicate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor.
2
A1
Device Address Select Pin 1. This pin determines the intermediate bit of the device address required to communicate
using the 2-wire interface. The A1 pin has an on-chip pull-down resistor.
3
A2
Device Address Select Pin 2. This pin determines the MSB of the device address required to communicate using the
2-wire interface. The A2 pin has an on-chip pull-down resistor.
4
V
CC
Supply Voltage.
5
WP
Write Protect Control Pin. This pin is a CMOS compatible input. When LOW, Write Protection is enabled preventing
any Write operation. When HIGH, various areas of the memory can be protected using the Block Lock bits BL1 and
BL0. The WP
pin has an on-chip pull-down resistor, which enables the Write Protection when this pin is left floating.
6
SCL
Serial Clock. This is a TTL compatible input pin. This input is the 2-wire interface clock controlling data input and output
at the SDA pin.
7
SDA
Serial Data. This pin is the 2-wire interface data into or out of the device. It is TTL
compatible when used as an input, and it is Open Drain when used as an output. This pin requires an external pull up
resistor.
8
I
OUT
Current Generator Output. This pin sinks or sources current. The magnitude and direction of the current is fully
programmable and adaptive. The resolution is 8 bits.
9, 10,
12,13,14
NC
No Connect.
11
V
SS
Ground.
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